VLSI Electronic Design Automation Tools Lab

We work hard to make our students happy and useful to the industry.

We create new knowledge and new EDA Tools.

We strive to turn our designs into pieces of art, and we enjoy fine art whenever available.

A piece of cyber art we would like to share with you: Channel Routing by an artist !

Our Lab environment supports graduate research, and completion of homework and project assignments for the under/grad courses offered by the EECS Department,

• Computational Aspects of VLSI
• Compaction in VLSI Design
• Routing in VLSI Design
• VLSI Channel Routing

These courses include six homeworks whose completion creates tools needed by the final project, which in turn produces a working tool for one of the VLSI physical design phases. All in ten weeks, the hands on computer work carries 60% of the grade points.

Our DAT Library supports our own dedicated Genetic Algorithm System and our own Neural Network Simulator, which both are the first of its kind able to route channels with cyclic vertical constraints. We take some pride in being the first there.